Controlling Zynq PL Clocks in Linux Userspace

The Xilinx Zynq Ultrascale devices seem to have this covered, but I struggled to find much info on how to do this with the Zynq 7000 parts. Here’s my notes on both platforms.

With a 4.19 kernel, the Xilinx PL clock enabler (XILINX_FCLK) is the driver you need. This will expose any compatible = “xlnx,fclk” device-tree nodes to userspace through sysfs. On Zynq this is something like

# echo 150000000 > /sys/devices/soc0/fclk0/set_rate
# cat /sys/devices/soc0/fclk0/set_rate
142857142  # obviously some PLL rounding to deal with

on ZynqMP

# echo 150000000 > /sys/devices/platform/fclk0/set_rate
# cat /sys/devices/platform/fclk0/set_rate
133333332  # obviously some PLL rounding to deal with

The ZynqMP dtsi’s already have fclk nodes supplied from zynqmp-clk-ccf.dtsi. My Zynq dts didn’t (probably because it was branched many years ago…) but they can be added like:

fclk0: fclk0 {
    status = "okay";
    compatible = "xlnx,fclk";
    clocks = <&clkc 15>;
};

The PL clocks on the Zynq are <&clkc 15>, <&clkc 16>, <&clkc 17> and <&clkc 18>. On the ZynqMP they are <&zynqmp_clk PL0_REF> etc. (if you #include <dt-bindings/clock/xlnx-zynqmp-clk.h>).

If you don’t want to set clock frequencies from userspace, you can use ‘assigned-clocks’ in any device tree node that seems relevant.

&custom-thing {
    assigned-clocks = <&clkc 15>, <&clkc 16>;
    assigned-clock-rates = <250000000>,
                           <100000000>;
};

Hope this saves someone else some time.

Cormorant Power Consumption

I’ve been a bit slow testing my Cormorant prototypes over the last few months. I have managed to complete the drivers for the IMU sensors and the data radio which cover most of the important hardware devices, so I thought now would be a good time to measure the power consumption. This is not just one simple number however, as Cormorant has many peripheral devices with many configurations each consuming different amounts of power.

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Cormorant. A New FPGA Based Autopilot

It has been a few years since I first assembled a prototype flight controller built around an FPGA, having been thoroughly distracted by work and thesis writing it’s about time I updated the design. So I hereby present Cormorant!

The concept is the same as before: motion sensors, actuator control, communication and of course the FPGA. All of these have come a long way since my original ProASIC3 design, and CPU/FPGA “SoCs” have become common. This new design centres around a SmartFusion2 SoC which uses the FPGA fabric of an igloo2 paired with a Cortex-M3 CPU.

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Processing Architectures

So I was listening to a recent episode of The Amp Hour; “An off-the-cuff radio show and podcast for electronics enthusiasts and professionals“, and Chris & Dave got onto the topic of custom logic implemented in an FPGA vs a hard or soft core processor (around 57 minutes into episode 98). This is a discussion very close to my current work and I’m probably in a very small minority so I figure I should speak up. (more…)